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๐Ÿ—“๏ธ Apr 18, 2015โฑ๏ธ 4 min read

Hardware vs Software: F5 LTM to Software-Defined Load Balancing

Why replacing physical F5 BIG-IP appliances with virtual load balancers caused a 15,000 TPS SSL meltdown, and how we engineered a hybrid load balancing architecture.

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โ€œSoftware-defined load balancing gives you instant API agility. Physical F5 hardware gives you dedicated ASIC crypto horsepower. Replacing physical F5 appliances with virtual VMs without benchmarking SSL handshake throughput will melt your hypervisor CPUs.โ€

In early 2015, during my tenure as Technical Lead at Wipro, we were modernizing the web application infrastructure for a major retail bank.

The perimeter load balancing architecture was anchored by high-end physical F5 BIG-IP 10200v hardware appliances. These physical boxes contained dedicated ePVA (embedded Packet Velocity Accelerator) ASICs engineered specifically for hardware SSL decryption and SYN-flood mitigation.

A cloud transformation consultant joined the project and made a bold proposal:

โ€œPhysical hardware is legacy. We should replace all F5 BIG-IP appliances with virtual software load balancer VMs running inside the hypervisor to achieve 100% software-defined elasticity.โ€

It sounded modern. It sounded agile.

It almost destroyed the bankโ€™s payday operations.


The Hype vs. The CPU Limit

The consultantโ€™s team deployed virtual load balancer appliances (vADCs) on standard x86 hypervisor nodes, replacing the physical F5 hardware endpoints for the primary online banking portal.

During light weekday testing (500 concurrent users), the virtual load balancers performed smoothly. The team declared victory and migrated 100% of production traffic to the software VMs on Thursday evening.

On Friday at 5:00 PMโ€”payday for millions of bank customersโ€”traffic surged.


The Mess: The Payday SSL Meltdown

At 5:15 PM, incoming web traffic reached 15,000 active SSL transactions per second (TPS).

Within two minutes, the ESXi host CPUs hosting the virtual load balancer VMs hit 100% utilization.

# Hypervisor CPU metrics during the Friday payday traffic spike
esxtop -> %USED: 99.8% | %READY: 18.4% (Severe CPU Scheduling Latency)
# F5 Virtual Appliance Log: SSL Handshake Timeout -> 40% Packet Loss

Decrypting RSA 2048-bit SSL certificates requires massive mathematical compute. Physical F5 appliances handle this in dedicated crypto ASICs without touching the main CPU. Virtual software appliances must compute RSA encryption using standard x86 CPU instructions.

At 15,000 TPS, the x86 hypervisor host CPUs were completely overwhelmed by SSL handshake calculations.

The consultant tried to fix it on the fly by allocating more vCPUs to the load balancer VMs (increasing from 4 vCPUs to 12 vCPUs).

That made things worse.

Adding more vCPUs increased hypervisor CPU scheduling latency (%READY time went from 4% to 18.4%). The ESXi scheduler struggled to find 12 free physical cores simultaneously, causing the virtual load balancers to stall for hundreds of milliseconds between packet arrivals.

10,000 active banking customers were locked out of their online accounts on payday evening.


The Solution: The Hybrid Edge-and-Overlay Architecture

We pulled the virtual load balancers out of the perimeter path, failed back to the physical F5 BIG-IP appliances, and established a Hybrid Load Balancing Architecture.

# Hybrid Load Balancing Architecture Model

| Tier                   | Technology                          | Primary Function                                                | Throughput Capability |
| ---------------------- | ----------------------------------- | --------------------------------------------------------------- | --------------------- |
| **Public Perimeter**   | Physical F5 BIG-IP (ePVA ASICs)     | Hardware SSL Termination, DDoS Mitigation, SYN Flood Protection | 40 Gbps / 100,000 TPS |
| **Internal App Tiers** | Virtual Load Balancers (NSX / vADC) | East-West Micro-routing, API Auto-Scaling, HTTP Health Probes   | 2 Gbps / 5,000 TPS    |
# Hardware SSL Offload Verification on Physical F5 BIG-IP
tmsh show sys hardware | grep -i epva
# Output: ePVA Hardware Acceleration: ACTIVE [15,000 TPS Offloaded to ASIC]

By placing physical F5 appliances at the public edge:

  1. Hardware SSL Termination: Physical F5 ASICs terminated SSL/TLS handshakes at the edge, handing unencrypted (or lightweight re-encrypted) HTTP traffic to internal network tiers.
  2. DDoS & SYN Guard: F5 hardware SYN-cookies absorbed perimeter attacks without impacting hypervisor compute.
  3. Agile Internal Routing: Software load balancers were deployed inside the virtual application tiers, where traffic volumes were lower and API-driven auto-scaling provided real value.

The Impact

  • Zero CPU Saturation: Reduced hypervisor host CPU utilization from 100% to a stable 15%.
  • Payday Scale: Successfully processed 25,000+ peak SSL TPS during subsequent payday traffic surges without a single dropped transaction.
  • Optimal Cost-Performance: Retained hardware performance where crypto math mattered, while gaining software agility inside internal application zones.

Key Takeaway

Architect for Workload Requirements, Not Hype.

Never replace hardware-accelerated appliances with software virtual machines without benchmarking high-frequency SSL crypto math and packet rates. Use physical hardware appliances with dedicated ASICs (like F5 BIG-IP) at the public edge for high-throughput SSL termination and DDoS protection, while deploying lightweight software load balancers inside virtual application tiers for API agility.


Architecture and decisions: mine. Debugging sessions at odd hours: mine. AI assistance: structure, syntax, first draft. โ€” Sachin

SKS

Sachin Kumar Sharma

Associate Director (Infrastructure & Cloud Architecture Strategy) | 20+ Yrs Exp

Architecting resilient multi-cloud enterprise landing zones, SDN overlay fabrics, DevSecFinOps automation pipelines, and autonomous Agentic AI platforms.

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